# LabWired v0.25.0 includes the STM32H563 chip model.
# Zephyr v4.4 startup also enables DCACHE1 at the address in ST's CMSIS header.
# This uses LabWired's existing cache-control stub. It does not model cache
# contents, hit/miss behavior, coherency, or cache-dependent timing.
name: "cmsis-zephyr-nucleo-h563zi"
chip: "stm32h563"
peripherals:
  - id: "dcache1"
    type: "dcache"
    base_address: 0x40031400
    size: "1KB"