A registered peripheral model runs in the engine: the firmware talks to it over the real bus and gets device-accurate responses.
Quad 3-state buffer with a PER-GATE active-low OE (core/configs/devices/74hc125.yaml), 9 ns. The four buffers gate independently, which is what makes it a bus driver. NOT modelled: LVT vs HC input thresholds — SN74LVTH125 is this model with different levels.
Simulated device model
Built from the datasheet. Implemented from the part’s register documentation and exercised by automated tests. Nothing physical was ever placed next to it.
GPIO_GROUP
[object Object]
| Pin | Type | Role |
|---|---|---|
A1 | input | — |
Y1 | tri_state | — |
OE1 | input | — |
A2 | input | — |
Y2 | tri_state | — |
OE2 | input | — |
A3 | input | — |
Y3 | tri_state | — |
OE3 | input | — |
A4 | input | — |
Y4 | tri_state | — |
OE4 | input | — |
VCC | power_in | — |
GND | power_in | — |
Modelled from Nexperia 74HC125 datasheet.